上海兆芯集成电路有限公司（以下简称“兆芯”）是成立于2013年的国资控股公司，总部位于上海张江，在北京、西安、武汉、深圳等地均设有研发中心和分支机构，公司拥有大批具备硕士、博士学历的专职研发人员。

兆芯是国内领先的芯片设计厂商，同时掌握中央处理器、图形处理器、芯片组三大核心技术，拥有三大核心芯片及相关IP的完全自主设计研发能力，全部研发环节透明可控。

兆芯致力于研发中国自主知识产权的核心处理器芯片。兆芯自主研发的中央处理器基于国际主流的x86指令集，产品性能国内领先，广泛应用于台式机、笔记本、一体机、存储服务器、磁盘阵列、工控整机等多种形态产品的设计生产。

采用兆芯通用CPU的多品牌台式电脑、笔记本电脑均已量产并完全达到成熟产品标准，且兼容性出色，可极大程度避免用户在迁移转换中的障碍。目前，兆芯平台整机已在党政军办公、信息化等国家重点系统和工程中得到积极推广和好评。国家“十二五”科技创新成就展期间，社会各界对兆芯通用CPU及整机、服务器等产品更予以了高度关注和肯定。

在国内全产业链整合方面，兆芯始终保持高度开放的合作态度，与来自芯片制造、封装测试、整机制造、固件开发、操作系统及软件开发、系统集成等环节的国内领军企业均形成密切的合作关系，共同为扩大、完善产业生态不遗余力。

凭借业内领先的性能表现及在相关领域取得的突出成果，兆芯通用CPU屡获殊荣。兆芯自主研发的开先ZX-C系列处理器先后荣获“第18届中国国际工业博览会金奖”、“第十一届（2016年度）中国半导体创新产品和技术”和“2017年度大中华IC设计成就奖”三大奖项；开先KX-6000系列处理器采用16nm工艺，主频达3.0GHz，兼容x86指令集，支持双通道DDR4-3200内存，支持4K视频解码，性能更加出色，一举荣获“第20届中国国际工业博览会金奖”，得到行业高度认可。

目前，兆芯通用CPU软硬件兼容性优秀，生态系统和产业链日趋完备，已可满足绝大多数国家关键领域的办公应用。兆芯将持续发挥自身核心优势，协同产业链伙伴共谋发展，为推动我国信息产业的整体发展不断贡献力量。

兆芯集成电路2020校园招聘职位：

网申地址：http://campus.51job.com/zhaoxin2020/job.html

招聘职位：

CPU/SOC-逻辑设计部

CPUBJ-01 ASIC Design Engineer(X86/SOC)

【Responsibilities】

1. X86 CPU /Chipset/SOC Design development

2. Timing verification, logic / physical synthesis, formal verification, and etc.

3. System verification, debugging and performance analyzing

4. Functional behavior model development; 

5. Function verification vectors development and debugging;

6. Emulation verification and debugging.

 

【Requirements】

1. MS/PHD in Microelectronic, Computer Science, Communication, EE, Automation and related;

2. Knowledge of digital circuit design, computer system architecture;

3. Familiar with Verilog/VHDL, and behavior modeling;

4. Experience with Design tools such as simulator, logic synthesis;

5. Strong problem solving and debugging skills; 

6. Good English language skill; 

7. Knowledge of X86 architecture is a plus;

8. Knowledge of C/C++ is a plus;

 

CPU/SOC-逻辑设计部

CPUBJ-02 ASIC Verification Engineer (X86/SOC)

【Responsibilities】

1. ASIC design verification methodology research and development;

2. Verification system development and maintenance;

3. Verification flow and execution ownership. 

4. Verification system buildup and debugging;

5. Function vector develop and debugging, coverage analysis and improvement;

6. Function modeling/monitor/assertion and script develop

 

 

【Requirements】

1. MS/PHD in Microelectronic, Computer Science, Communication, EE, Automation and related

2. Knowledge of digital circuit design and computer system architecture

3. Familiar with Verilog/VHDL, SystemVerilog and C/C++

4. Experience with simulator such as NC/VCS

5. Good team work; strong problem solving and debugging skills; 

6. Good English communication skill. 

7. Knowledge of Unix platform and csh. Perl or python and tcl programming is a plus

8. Knowledge of X86 architecture is a plus

9. Knowledge of UVM system is a plus

 

CPU/SOC-逻辑设计部

CPUBJ-03 FPGA/Emulation Engineer (X86/SOC)

【Responsibilities】

1. FPGA emulation solution definition and FPGA implementation for chipset/X86 SOC function validation.

2. Design porting from ASIC to FPGA

3. FPGA design simulation and debugging

4. FPGA implementation flow, synthesis, P&R, timing, .etc 

5. FPGA on board debugging

【Requirements】

1. MS in Electronics

2. Knowledge of digital circuit design, and computer system architecture

3. Familiar with Verilog/VHDL

4. Familiar with Xilinx Series FPGA device structure

5. Experience with FPGA implementation tools such as synplify, vivado, protocompiler .etc;

6. Good team work; strong problem solving and debugging skills; 

7. Good English communication skill. 

8. Knowledge of Unix platform and csh. Perl and tcl programming is a plus

9. Knowledge of X86 architecture is a plus

 

CPU/SOC-CPU架构设计部

CPUBJ-04 CPU Architecture Engineer

【Responsibilities】

1. Developing the module design and architecture of a complex microprocessor in deep 

sub-micron process technology

2. Developing the CPU microarchitecture based on function/performance/power requirements

3. Improving the CPU architecture for optimized performance and power       

4. Developing server processor and system architecture   

5. CPU performance/power evaluation

6. CPU function/performance modeling

 

【Requirements】

1. MS/PHD in Microelectronic, Computer Science or related

2. Complete understanding of advanced CPU architecture and design techniques

3. Significant experience and knowledge with CPU design and improvement

4. Good understanding of OS and other general software tools 

5. Server system development experience is a plus 

6. Strong problem solving and debugging skills

7. Good English language skill

8. Knowledge of C/C++ is a plus

9. Knowledge of processor modeling is a plus

CPU/SOC-物理设计部

CPUBJ-05 ASIC Physical Design Engineer

 

【职位描述】

1. 高性能、低功耗x86 CPU/SOC数字后端设计收敛及签核验证

2. 先进工艺物理设计方法学研究及流程开发维护

【要求】

1. 电子工程、微电子、集成电路或相关专业，硕士学历;

2.  具备良好的沟通表达力和团队协作能力，踏实勤奋，积极主动，善于学习，乐于创新;

3.  有良好的英语听说读写技能;

4.  有数字后端先进工艺物理设计相关经验者优先

5.  有TCL/Shell/Perl/Python 等脚本语言编写经验者优先

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